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Large language models can now power capable software agents, yet real‑world success comes from disciplined engineering rather than flashy frameworks. Most reliable agents are built from simple, composable patterns instead of heavy abstractions.


The talk will introduce patterns to add complexity and autonomy only when it pays off. Attendees should leave with a practical decision framework for escalating from a single prompt to multi‑step agents, also keeping in mind guardrails for shipping trustworthy, cost‑effective agents at scale. 

Author:

Sushant Mehta

Research Engineer
Google Deepmind
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Sushant Mehta

Research Engineer
Google Deepmind

Author:

Sherman Ikemoto

Group Director
Cadence

Sherman Ikemoto is the Sales Development Group Director at Cadence Design Systems, where he leads global business development for the innovative Reality DC Digital Twin solution. With a passion for addressing challenges in data center design, performance, and sustainability, Sherman brings extensive expertise to the forefront of this critical industry. Previously, Sherman served as Managing Director and Board Member at Future Facilities, the pioneer of the original data center Digital Twin, and as North America Sales and Marketing Director at Flomerics, where he helped introduce computational fluid dynamics modeling to electronics cooling design. During his tenure at Future Facilities, Sherman was a sought-after speaker at prominent industry events like ITW, Data Center World, Uptime Symposium, and Data Center Dynamics. Sherman holds a Bachelor of Science in Mechanical Engineering (BSME) from San Jose State University, where he was a member of the Tau Beta Pi engineering honor society, and a Master of Science in Mechanical Engineering (MSME) from Santa Clara University. His career reflects a deep commitment to advancing sustainable and efficient technologies for the data center industry.

... read more

Sherman Ikemoto

Group Director
Cadence

Sherman Ikemoto is the Sales Development Group Director at Cadence Design Systems, where he leads global business development for the innovative Reality DC Digital Twin solution. With a passion for addressing challenges in data center design, performance, and sustainability, Sherman brings extensive expertise to the forefront of this critical industry. Previously, Sherman served as Managing Director and Board Member at Future Facilities, the pioneer of the original data center Digital Twin, and as North America Sales and Marketing Director at Flomerics, where he helped introduce computational fluid dynamics modeling to electronics cooling design. During his tenure at Future Facilities, Sherman was a sought-after speaker at prominent industry events like ITW, Data Center World, Uptime Symposium, and Data Center Dynamics. Sherman holds a Bachelor of Science in Mechanical Engineering (BSME) from San Jose State University, where he was a member of the Tau Beta Pi engineering honor society, and a Master of Science in Mechanical Engineering (MSME) from Santa Clara University. His career reflects a deep commitment to advancing sustainable and efficient technologies for the data center industry.

Revterra’s Kinetic Stabilizer is engineered to handle the massive and volatile power swings demanded by large-scale AI workloads. AI is bottlenecked by infrastructure and requires a rapidly scalable, high-performance power quality solution that can be deployed without fear of supply chain disruption. Our battery-free technology provides a stable bridge between the grid and AI loads with a physically instantaneous, passive response—no power electronics required. Unlike conventional solutions, the Kinetic Stabilizer offers unmatched cost-effectiveness on a per-kW basis and a functionally infinite cycle life, free from the constraints of chemical storage.

Author:

Ben Jawdat

Founder & CEO
Revterra

Ben Jawdat is the founding CEO of Revterra, where he is working to commercialize a kinetic stabilizer solution to solve power quality challenges at AI datacenters and other commercial/industrial sites. Prior to starting Revterra, he worked on the development of new superconducting materials at the University of Houston where he received his PhD in physics, and completed postdoctoral studies at the Air Force Research Laboratory and Rice University.

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Ben Jawdat

Founder & CEO
Revterra

Ben Jawdat is the founding CEO of Revterra, where he is working to commercialize a kinetic stabilizer solution to solve power quality challenges at AI datacenters and other commercial/industrial sites. Prior to starting Revterra, he worked on the development of new superconducting materials at the University of Houston where he received his PhD in physics, and completed postdoctoral studies at the Air Force Research Laboratory and Rice University.

Flexnode’s approach delivers a strategic advantage over traditional data center construction by transferring complexity off the job site and into a controlled manufacturing environment. Our modules are engineered for speed, scalability, and geographic flexibility—purpose built to support the rapidly evolving demands of AI and high-performance compute workloads. By industrializing the data center, we ensure repeatable, high-quality outcomes that can be rapidly deployed with minimal on-site work.

Author:

Zac Kostura

EVP of Product Strategy and Solution Development
Flexnode

As Executive Vice President of Product Strategy and Solution Development at Flexnode, Zak leads product strategy for next-generation data center infrastructure designed to meet the demands of high-performance computing and AI workloads. His focus is on bridging technology, design, and business strategy to shape modular solutions that redefine how compute infrastructure is deployed and scaled.

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Zac Kostura

EVP of Product Strategy and Solution Development
Flexnode

As Executive Vice President of Product Strategy and Solution Development at Flexnode, Zak leads product strategy for next-generation data center infrastructure designed to meet the demands of high-performance computing and AI workloads. His focus is on bridging technology, design, and business strategy to shape modular solutions that redefine how compute infrastructure is deployed and scaled.

As AI algorithms become more complex, they consume disproportionately greater run-time and energy. This makes meeting performance or efficiency goals require some level of hardware acceleration. The highest levels of performance and efficiency are achieved with custom hardware. Traditional hardware design and verification methodologies are labor-intensive and time-consuming and are not a good match for rapidly evolving AI technologies.

We will introduce the application of High-Level Synthesis (HLS) for automating many of the hardware design tasks involved in creating a bespoke accelerator. Using HLS, popular machine learning frameworks, and Quantize-Aware Training, we can build highly optimized and bit precise hardware, targeting ASIC or FPGA implementations.

Author:

Cameron Villone

HLS Technologist
Siemens

 Cameron Villone is a High-Level Synthesis Technologist working with the Catapult High-Level Synthesis product management and marketing team, focusing on AI hardware deployment. He previously worked as a product marketing engineer for PowerPro, Siemens’ power optimization and analysis product. He held previous roles at Texas Instruments and General Motors. Cameron studied and graduated from Rochester Institute of Technology, obtaining both a bachelor's and master's degree in electrical engineering, focusing on Robotics, Embedded Systems, and Computer Vision.

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Cameron Villone

HLS Technologist
Siemens

 Cameron Villone is a High-Level Synthesis Technologist working with the Catapult High-Level Synthesis product management and marketing team, focusing on AI hardware deployment. He previously worked as a product marketing engineer for PowerPro, Siemens’ power optimization and analysis product. He held previous roles at Texas Instruments and General Motors. Cameron studied and graduated from Rochester Institute of Technology, obtaining both a bachelor's and master's degree in electrical engineering, focusing on Robotics, Embedded Systems, and Computer Vision.

Semiconductor development faces increasing complexity, faster timelines, and fierce competition, exposing the limitations of traditional EDA tools. In response, AI Agents, powered by LLMs and advanced algorithms, are emerging as next-gen solutions. This session explores how these agents surpass conventional automation by independently managing tasks like hardware modeling, constraint solving, debugging, testbench creation, and design optimization. We'll cover real-world use cases showing how AI Agents deliver improved productivity, design quality, and time-to-market, including their ability to autonomously detect bugs and optimize RTL designs.

Author:

Mehir Arora

Founding Engineer
ChipAgents

Mehir Arora is a founding engineer at ChipAgents, a company at the forefront of integrating agentic AI into Electronic Design Automation (EDA) workflows. Graduated from UC Santa Barbara, Mehir has contributed to advancing state-of-the-arts in AI methodologies, including a paper presented at ICML 2024. At ChipAgents, he focuses on developing agentic AI tools that enhance chip design and verification processes, aiming to significantly improve efficiency and productivity in semiconductor engineering. 

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Mehir Arora

Founding Engineer
ChipAgents

Mehir Arora is a founding engineer at ChipAgents, a company at the forefront of integrating agentic AI into Electronic Design Automation (EDA) workflows. Graduated from UC Santa Barbara, Mehir has contributed to advancing state-of-the-arts in AI methodologies, including a paper presented at ICML 2024. At ChipAgents, he focuses on developing agentic AI tools that enhance chip design and verification processes, aiming to significantly improve efficiency and productivity in semiconductor engineering.